CMOS circuit verification with symbolic switch-level timing simulation. - McDonald, C.B (IEEE Transactions on computer-aided design of integrated circuits and systems)
Symbolic switch-level simulation has been extensively applied to the functional verification of complementary metal-oxide-semiconductor (CMOS) circuitry. We have extended this technique to account for real-valued data-dependent delay values and have developed a novel mechanism for symbolically computing data-dependent Elmore delays. We present our symbolic simulation and delay calculation algorithms and discuss their application to the timing and functional verification of full-custom transistor-level CMOS circuitry