CMOS circuit verification with symbolic switch-level timing simulation.

CMOS circuit verification with symbolic switch-level timing simulation.

Symbolic switch-level simulation has been extensively applied to the functional verification of complementary metal-oxide-semiconductor (CMOS) circuitry. We have extended this technique to account for real-valued data-dependent delay values and have developed a novel mechanism for symbolically compu...

詳細記述

書誌詳細
出版年:IEEE Transactions on computer-aided design of integrated circuits and systems 20, 3 (2001).
第一著者: McDonald, C.B
フォーマット: 論文
言語:English
主題:
CMOS circuit verification.
Data-dependent Elmore delays.
Delay calculation algorithms.
Full-custom transistor-level CMOS circuitry.
Real-valued data-dependent delay values.
Symbolic switch-level timing simulation.