Citazione Stile APA (7a Edizione)

McDonald, C. CMOS circuit verification with symbolic switch-level timing simulation. IEEE Transactions on computer-aided design of integrated circuits and systems.

Citazione stile Chigago Style (17a edizione)

McDonald, C.B. "CMOS Circuit Verification with Symbolic Switch-level Timing Simulation." IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems .

Citatione MLA (9a ed.)

McDonald, C.B. "CMOS Circuit Verification with Symbolic Switch-level Timing Simulation." IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems, .