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   <subfield code="a">Ravi, S.</subfield>
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   <subfield code="a">Testing of core-based systems-on-a-chip.</subfield>
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   <subfield code="a">pp. 426-439</subfield>
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   <subfield code="a">Available techniques for testing of core-based systems-on-a-chip (SOCs) do not provide a systematic means for synthesizing low-overhead test architectures and compact test solutions. In this paper, we provide a comprehensive framework that generates low-overhead compact test solutions for SOCs. First, we develop a common ground for addressing issues such as core test requirements, core access, and testing hardware additions. For this purpose, we introduce finite-state automata (FSA) for modeling tests, transparency modes, and testing hardware behavior. In many cases, the tests repeat a basic set of test actions for different test data that can again be modeled using FSA. While earlier work can derive a single symbolic test for a module in a register-transfer level (RTL) circuit as a finite-state automaton, this work extends the methodology to the system level and additionally contributes a satisfiability-based solution to the problem of applying a sequence of tests phased in time. This problem is known to be a bottleneck in testability analysis not only at the system level, but also at the RTL. Experimental results show that the system-level average area overhead for making SOCs testable with our method is only 4.5%, while achieving an average test application time reduction of 80% over recent approaches. At the same time, it provides 100% test coverage of the precomputed test sets/sequences of the embedded cores</subfield>
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   <subfield code="a">Core access.</subfield>
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   <subfield code="a">Core-based systems-on-a-chip.</subfield>
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   <subfield code="a">Finite-state automata.</subfield>
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   <subfield code="a">Hardware additions.</subfield>
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   <subfield code="a">Hardware behavior.</subfield>
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   <subfield code="a">Register-transfer level circuit.</subfield>
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   <subfield code="a">Satisfiability-based solution.</subfield>
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   <subfield code="a">Symbolic test.</subfield>
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   <subfield code="a">System-level average area overhead.</subfield>
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   <subfield code="a">Test application time reduction.</subfield>
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   <subfield code="a">Testability analysis.</subfield>
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   <subfield code="a">Transparency modes.</subfield>
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  <datafield tag="773" ind1="0" ind2=" ">
   <subfield code="t">IEEE Transactions on computer-aided design of integrated circuits and systems</subfield>
   <subfield code="g">20, 3 (2001).</subfield>
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