Cita APA (7th ed.)

Chung-Yang Huan. Using word-level ATPG and modular arithmetic constraint-solving techniques for assertion property checking. IEEE Transactions on computer-aided design of integrated circuits and systems.

Cita Chicago (17th ed.)

Chung-Yang Huan. "Using Word-level ATPG and Modular Arithmetic Constraint-solving Techniques for Assertion Property Checking." IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems .

Cita MLA (9th ed.)

Chung-Yang Huan. "Using Word-level ATPG and Modular Arithmetic Constraint-solving Techniques for Assertion Property Checking." IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems, .