00000cab a22000003a 4500 UP-99796217609500609 Buklod 20231007234342.0 m |o d | ta 101013s xx d | ||r ||||| || DENGII eng Iyengar, V. System-on-a-chip test scheduling with precedence relationships, preemption, and power constraints. pp. 1088-1094 Test scheduling is an important problem in system-on-a-chip (SOC) test automation. Efficient test schedules minimize the overall system test application time, avoid test resource conflicts, and limit power dissipation during test mode. In this paper, we present an integrated approach to several test scheduling problems. We first present a method to determine optimal schedules for reasonably sized SOCs with precedence relationships, i.e., schedules that preserve desirable orderings among tests. We also present an efficient heuristic algorithm to schedule tests for large SOCs with precedence constraints in polynomial time. We describe a novel algorithm that uses preemption of tests to obtain efficient schedules for SOCs. Experimental results for an academic SOC and an industrial SOC show that efficient test schedules can be obtained in reasonable CPU time SOCs. Desirable orderings. Embedded core testing. Heuristic algorithm. Polynomial time. Power constraints. Power dissipation. Precedence relationships. Preemption. System-on-a-chip test automation. Test resource conflicts. Test schedules. IEEE Transactions on computer-aided design of integrated circuits and systems 21, 9 (2002). FO UPD DENG-II Article