Cita APA

Iyengar, V. System-on-a-chip test scheduling with precedence relationships, preemption, and power constraints. IEEE Transactions on computer-aided design of integrated circuits and systems.

Citación estilo Chicago

Iyengar, V. "System-on-a-chip Test Scheduling with Precedence Relationships, Preemption, and Power Constraints." IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems .

Cita MLA

Iyengar, V. "System-on-a-chip Test Scheduling with Precedence Relationships, Preemption, and Power Constraints." IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems, .