Iyengar, V. System-on-a-chip test scheduling with precedence relationships, preemption, and power constraints. IEEE Transactions on computer-aided design of integrated circuits and systems.
Chicago-viite (17. p.)Iyengar, V. "System-on-a-chip Test Scheduling with Precedence Relationships, Preemption, and Power Constraints." IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems .
MLA-viite (9. p.)Iyengar, V. "System-on-a-chip Test Scheduling with Precedence Relationships, Preemption, and Power Constraints." IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems, .
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