A timing-constrained simultaneous global routing algorithm.

A timing-constrained simultaneous global routing algorithm.

Proposed in this paper is a new approach for VLSI interconnect global routing that can optimize both congestion and delay, which are often competing objectives. The authors' approach provides a general framework that may use any single-net routing algorithm and any delay model in global routing...

Täydet tiedot

Bibliografiset tiedot
Julkaisussa:IEEE Transactions on computer-aided design of integrated circuits and systems 21, 9 (2002).
Päätekijä: Jiang Hu
Aineistotyyppi: Artikkeli
Kieli:English
Aiheet:
0.02 to 0.15 s.
VLSI.
Benchmark circuits.
Bisector line.
Cell boundaries.
Congestion.
Delay.
Interconnect global routing.
Network flow formulation.
Rip-up-and-reroute process.
Routing region.
Single-net routing algorithm.
Slideable Steiner node.
Soft edge.
Timing constraints.
Timing slack.