A timing-constrained simultaneous global routing algorithm.
Proposed in this paper is a new approach for VLSI interconnect global routing that can optimize both congestion and delay, which are often competing objectives. The authors' approach provides a general framework that may use any single-net routing algorithm and any delay model in global routing...
| Publicado en: | IEEE Transactions on computer-aided design of integrated circuits and systems 21, 9 (2002). |
|---|---|
| Autor principal: | |
| Formato: | Artículo |
| Lenguaje: | English |
| Materias: |