A timing-constrained simultaneous global routing algorithm.
Proposed in this paper is a new approach for VLSI interconnect global routing that can optimize both congestion and delay, which are often competing objectives. The authors' approach provides a general framework that may use any single-net routing algorithm and any delay model in global routing...
| Publicat a: | IEEE Transactions on computer-aided design of integrated circuits and systems 21, 9 (2002). |
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| Autor principal: | |
| Format: | Article |
| Idioma: | English |
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