An instruction-level energy model for embedded VLIW architectures.

An instruction-level energy model for embedded VLIW architectures.

In this paper, an instruction-level energy model is proposed for the data-path of very long instruction word (VLIW) pipelined processors that can be used to provide accurate power consumption information during either an instruction-level simulation or power-oriented scheduling at compile time. The...

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Bibliografski detalji
Izdano u:IEEE Transactions on computer-aided design of integrated circuits and systems 21, 9 (2002).
Glavni autor: Sami, M.
Format: Članak
Jezik:English
Teme:
VLIW.
Embedded architectures.
Four-issue core.
Instruction cache miss probability.
Instruction ordering.
Instruction-level energy model.
Instruction-level simulation.
Pipeline stall probability.
Pipelined processors.
Power consumption information.
Power-oriented scheduling.
Six-stage pipeline.
Software-level parameters.
Very long instruction.