Concurrent error detection schemes for fault-based side-channel cryptanalysis of symmetric block ciphers. - Karri, R.
Fault-based side-channel cryptanalysis is very effective against symmetric and asymmetric encryption algorithms. Although straightforward hardware and time redundancy-based concurrent error detection (CED) architectures can be used to thwart such attacks, they entail significant overheads (either area or performance). The authors investigate systematic approaches to low-cost low-latency CED techniques for symmetric encryption algorithms based on inverse relationships that exist between encryption and decryption at algorithm level, round level, and operation level and develop CED architectures that explore tradeoffs among area overhead, performance penalty, and fault detection latency. The proposed techniques have been validated on FPGA implementations of Advanced Encryption Standard (AES) finalist 128-bit symmetric encryption algorithms.
Keywords: Advanced Encryption Standard finalist 128-bit symmetric encryption algorithms; FPGA implementations; MARS encryption; RC6 symmetric block cipher encryption; Rijndael symmetric block cipher; Serpent block cipher; Algorithm level; Area overhead; Asymmetric encryption algorithms; Concurrent error detection schemes; Decryption; Fault detection latency; Fault-based side-channel cryptanalysis; Inverse relationships; Low-cost low-latency CED techniques; Operation level; Performance penalty; Round level; Symmetric block ciphers; Symmetric encryption algorithms