RS-FDRA A register-sensitive software pipelining algorithm for embedded VLIW processors.
The paper proposes a novel software-pipelining algorithm, Register-Sensitive Force-Directed Retiming Algorithm (RS-FDRA), suitable for optimizing compilers targeting embedded very large instruction word processors. The key difference between RS-FDRA and previous approaches is that this algorithm can...
| Publié dans: | IEEE Transactions on computer-aided design of integrated circuits and systems 21, 12 (2002). |
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| Format: | Article |
| Langue: | English |
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