APA-viite (7. p.)

Chun-Yao Wang. Automatic interconnection rectification for SoC design verification based on the port order fault model. IEEE Transactions on computer-aided design of integrated circuits and systems.

Chicago-viite (17. p.)

Chun-Yao Wang. "Automatic Interconnection Rectification for SoC Design Verification Based on the Port Order Fault Model." IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems .

MLA-viite (9. p.)

Chun-Yao Wang. "Automatic Interconnection Rectification for SoC Design Verification Based on the Port Order Fault Model." IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems, .