Timed compiled-code functional simulation of embedded software for performance analysis of SOC design.
A new timing generation method is proposed for the performance analysis of embedded software. The time stamp generation of input/output (I/O) accesses is crucial to performance estimation and architecture exploration in the timed functional simulation that simulates the whole design at a functional...
| Cyhoeddwyd yn: | IEEE Transactions on computer-aided design of integrated circuits and systems 22, 1 (2003). |
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| Prif Awdur: | |
| Fformat: | Erthygl |
| Iaith: | English |
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