Binkley, D. A CAD methodology for optimizing transistor current and sizing in analog CMOS design. IEEE Transactions on computer-aided design of integrated circuits and systems.
Chicago Style (17th ed.) CitationBinkley, D.M. "A CAD Methodology for Optimizing Transistor Current and Sizing in Analog CMOS Design." IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems .
MLA (9th ed.) CitationBinkley, D.M. "A CAD Methodology for Optimizing Transistor Current and Sizing in Analog CMOS Design." IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems, .
Warning: These citations may not always be 100% accurate.