APA citiranje

Binkley, D. A CAD methodology for optimizing transistor current and sizing in analog CMOS design. IEEE Transactions on computer-aided design of integrated circuits and systems.

Chicago Style (17th ed.) Citation

Binkley, D.M. "A CAD Methodology for Optimizing Transistor Current and Sizing in Analog CMOS Design." IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems .

MLA citiranje

Binkley, D.M. "A CAD Methodology for Optimizing Transistor Current and Sizing in Analog CMOS Design." IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems, .