Test pattern generation and clock disabling for simultaneous test time and power reduction.

Test pattern generation and clock disabling for simultaneous test time and power reduction.

Scan-based design has been widely used to transport test patterns in a system-on-a-chip (SOC) test architecture. Two problems that are becoming quite critical for scan-based testing are long test application time and high test power consumption. Previously, many efficient methods have been developed...

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Pubblicato in:IEEE Transactions on computer-aided design of integrated circuits and systems 22, 3 (2003).
Autore principale: Jih-Jeen Chen
Natura: Articolo
Lingua:English
Soggetti:
ATPG.
BIST.
DFT.
SoC test architecture.
Design for testability approach.
Low-power testing.
Multiple clock disabling technique.
Scan-based design.
System-on-a-chip.
Test application time.
Test pattern generation.
Test power dissipation.
Test set compaction.