00000cab a22000003a 4500 UP-99796217609500290 Buklod 20231007234344.0 m |o d | ta 101009s xx d | ||r ||||| || DENGII eng Jih-Jeen Chen Test pattern generation and clock disabling for simultaneous test time and power reduction. pp. 363-370 Scan-based design has been widely used to transport test patterns in a system-on-a-chip (SOC) test architecture. Two problems that are becoming quite critical for scan-based testing are long test application time and high test power consumption. Previously, many efficient methods have been developed to address these two problems separately. In this paper, we propose a novel method called the multiple clock disabling (MCD) technique to reduce test application time and test power dissipation simultaneously. Our method is made possible by cleverly modifying and integrating a number of existing techniques to generate a special set of test patterns that is suitable for a scan architecture based on the MCD technique. Experimental results for the International Symposium on Circuits and Systems (ISCAS) '85 and '89 benchmark circuits show that significant reduction on both test application time and power dissipation can be achieved compared to the conventional scan method. ATPG. BIST. DFT. SoC test architecture. Design for testability approach. Low-power testing. Multiple clock disabling technique. Scan-based design. System-on-a-chip. Test application time. Test pattern generation. Test power dissipation. Test set compaction. IEEE Transactions on computer-aided design of integrated circuits and systems 22, 3 (2003). FO Article