APA (7 ম সংস্করণ) উদ্ধৃতি

Jih-Jeen Chen. Test pattern generation and clock disabling for simultaneous test time and power reduction. IEEE Transactions on computer-aided design of integrated circuits and systems.

শিকাগো স্টাইল (17 তম সংস্করণ) উদ্ধৃতি

Jih-Jeen Chen. "Test Pattern Generation and Clock Disabling for Simultaneous Test Time and Power Reduction." IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems .

M.L.A (9 ম সংস্করণ) উদ্ধৃতি

Jih-Jeen Chen. "Test Pattern Generation and Clock Disabling for Simultaneous Test Time and Power Reduction." IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems, .