Jih-Jeen Chen. Test pattern generation and clock disabling for simultaneous test time and power reduction. IEEE Transactions on computer-aided design of integrated circuits and systems.
توثيق أسلوب شيكاغو (الطبعة السابعة عشر)Jih-Jeen Chen. "Test Pattern Generation and Clock Disabling for Simultaneous Test Time and Power Reduction." IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems .
توثيق جمعية اللغة المعاصرة MLA (الإصدار التاسع)Jih-Jeen Chen. "Test Pattern Generation and Clock Disabling for Simultaneous Test Time and Power Reduction." IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems, .
تحذير: قد لا تكون هذه الاستشهادات دائما دقيقة بنسبة 100%.