Jih-Jeen Chen. Test pattern generation and clock disabling for simultaneous test time and power reduction. IEEE Transactions on computer-aided design of integrated circuits and systems.
Chicago Style (17th ed.) CitationJih-Jeen Chen. "Test Pattern Generation and Clock Disabling for Simultaneous Test Time and Power Reduction." IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems .
MLA (9th ed.) CitationJih-Jeen Chen. "Test Pattern Generation and Clock Disabling for Simultaneous Test Time and Power Reduction." IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems, .
Warning: These citations may not always be 100% accurate.