Jih-Jeen Chen. Test pattern generation and clock disabling for simultaneous test time and power reduction. IEEE Transactions on computer-aided design of integrated circuits and systems.
शिकागो शैली (17वां संस्करण) प्रशस्ति पत्रJih-Jeen Chen. "Test Pattern Generation and Clock Disabling for Simultaneous Test Time and Power Reduction." IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems .
एमएलए (9वां संस्करण) प्रशस्ति पत्रJih-Jeen Chen. "Test Pattern Generation and Clock Disabling for Simultaneous Test Time and Power Reduction." IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems, .
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