A unified approach to reduce SOC test data volume, scan power and testing time.

A unified approach to reduce SOC test data volume, scan power and testing time.

We present a test resource partitioning (TRP) technique that simultaneously reduces test data volume, test application time, and scan power. The proposed approach is based on the use of alternating run-length codes for test data compression. We present a formal analysis of the amount of data compres...

詳細記述

書誌詳細
出版年:IEEE Transactions on computer-aided design of integrated circuits and systems 22, 3 (2003).
第一著者: Chandra, A.
フォーマット: 論文
言語:English
主題:
ATPG.
SoC test.
Alternating run-length codes.
Embedded core testing.
Formal analysis.
Scan power reduction.
Scan shifting.
Scan testing.
Switching activity.
System-on-a-chip testing.
Test application time reduction.
Test data compression.
Test data volume reduction.
Test resource partitioning technique.
Unified approach.