Methods for minimizing dynamic power consumption in synchronous designs with multiple supply voltages.
We address the problem of minimizing dynamic power consumption under performance constraints by scaling down the supply voltage of computational elements off critical paths. We assume that the number of possible supply voltages and their values are known for each computational element. We focus on s...
| Publicado no: | IEEE Transactions on computer-aided design of integrated circuits and systems 22, 3 (2003). |
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| Autor principal: | |
| Formato: | Artigo |
| Idioma: | English |
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