Random access at double the speed.

Unveiled at the IEEE's Symposium on VLSI Circuits, a novel dynamic memory architecture challenges static memory.

Détails bibliographiques

Publié dans:	IEEE spectrum 39, 8 (2002).
Auteur principal:	Geppert, N.
Format:	Article
Langue:	English
Sujets:	512 Kbit. ASIC. IBM demonstration chip. Architectural device. Circuit blocks. Dynamic memory architecture. Embedded DRAM. Macros. On-chip memory applications. Systems-on-chip. Write-back buffer.