Random access at double the speed.

Unveiled at the IEEE's Symposium on VLSI Circuits, a novel dynamic memory architecture challenges static memory.

Opis bibliograficzny

Wydane w:	IEEE spectrum 39, 8 (2002).
1. autor:	Geppert, N.
Format:	Artykuł
Język:	English
Hasła przedmiotowe:	512 Kbit. ASIC. IBM demonstration chip. Architectural device. Circuit blocks. Dynamic memory architecture. Embedded DRAM. Macros. On-chip memory applications. Systems-on-chip. Write-back buffer.