Design of packet-fair queuing schedulers using a RAM-based searching engine.

The implementation of packet-fair queuing (PFQ) schedulers, which aim at approximating the generalized processor sharing (GPS) policy, is a central issue for providing multimedia services with various quality-of-service (QoS) requirements in packet-switching networks. In the PFQ scheduler, packets a...

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Bibliografske podrobnosti
izdano v:	IEEE Journal on selected areas in communications 17, 6 (1999).
Glavni avtor:	Chao, H.J
Format:	Article
Jezik:	English
Teme:	FPGA chips. GPS policy. PFQ schedulers. QoS. RAM-based searching engine. Aging. Field programmable gate array. Generalized processor sharing policy. Hierarchical searching. Multimedia services. Overflow. Packet-fair queuing schedulers. Packet-switching network. Quality-of-service. Searching process. Shaper-scheduler. Tree data structure. Two-dimensional RSE architecture.