A 256-Kb Dual-VCC SRAM Building Block in 65-nm CMOS Process With Actively Clamped Sleep Transistor.

A 256-Kb Dual-VCC SRAM Building Block in 65-nm CMOS Process With Actively Clamped Sleep Transistor.

This paper addresses the stability problem of SRAM cells used in dense last level caches (LLCs). In order for the LLC not to limit the minimum voltage at which a processor core can run, a dual-VCC 256-Kb SRAM building block is proposed. A fixed high-voltage supply powers the cache which allows the u...

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Publié dans:IEEE Journal of solid state circuits 42, 1 (2007).
Auteur principal: Khellah, M.
Format: Article
Langue:English
Sujets:
1.2 V.
256 kBytes.
30 mW.
4.2 GHz.
64 MBytes.
65 nm.
85 C.
CMOS process.
SRAM building block.
SRAM cells stability.
Cache leakage power reduction.
Dual-Vcc processor.
Embedded level shifters.
Last level caches.
Processor core.
Processor power.
Sleep transistor.