Cita APA (7th ed.)

Khellah, M. A 256-Kb Dual-VCC SRAM Building Block in 65-nm CMOS Process With Actively Clamped Sleep Transistor. IEEE Journal of solid state circuits.

Cita Chicago (17th ed.)

Khellah, M. "A 256-Kb Dual-VCC SRAM Building Block in 65-nm CMOS Process With Actively Clamped Sleep Transistor." IEEE Journal of Solid State Circuits .

Cita MLA (9th ed.)

Khellah, M. "A 256-Kb Dual-VCC SRAM Building Block in 65-nm CMOS Process With Actively Clamped Sleep Transistor." IEEE Journal of Solid State Circuits, .