An 8.1-ns Column-Access 1.6-Gb/s 4 Multiplexed Data-Transfer Scheme. - Fujisawa, H.
Three circuit techniques for an 8.1-ns column-access 1.6-Gb/s/pin 512-Mb DDR3 SDRAM using 90-nm dual-gate CMOS technology were developed. First, an 8:4 multiplexed data-transfer scheme, which operates in a quasi-4-bit prefetch mode, achieves a 3.17-ns reduction in column-access time, i.e., from 11.3 to 8.13 ns. Second, a dual-clock latency counter reduces standby power by 22% and cycle time from 1.7 to 1.2 ns. Third, a multiple-ODT-merged output buffer enables selection of five effective-resistance values Rtt (20, 30, 40, 60, and 120 Omega) without increasing I/O capacitance. Based on these techniques, 1.6-Gb/s/pin operation with a 1.36-V power supply and a column latency of 7 was accomplished
Keywords: 1.2 ns; 1.36 V; 1.6 Gbits/s.; 120 ohm; 20 ohm; 30 ohm; 40 ohm; 60 ohm; 8.13 ns; 90 nm; DDR3 SDRAM; ZQ calibration; Data-transfer scheme; Dual-clock latency counter; Dual-gate CMOS technology