The Design and Implementation of the Massively Parallel Processor Based on the Matrix Architecture.

The Design and Implementation of the Massively Parallel Processor Based on the Matrix Architecture.

This paper describes the design and implementation of the massively parallel processor based on the matrix architecture which is suitable for portable multimedia applications. The proposed architecture in this paper achieves the high performance of 40 GOPS in the case of consecutive fixed-point 16-b...

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Sonraí bibleagrafaíochta
Foilsithe in:IEEE Journal of solid state circuits 42, 1 (2007).
Príomhchruthaitheoir: Noda, H.
Formáid: Alt
Teanga:English
Ábhair:
1 Mbit.
16 bit.
2 bit.
200 MHz.
250 mW.
90 nm.
CMOS technology.
SIMD.
SRAM.
Clock frequency.
Data registers.
Integrated circuits.
Matrix architecture.
Parallel processor.
Portable multimedia processors.
Power dissipation.
Switching network.