A 160K Gates - Lin, C.-C.
In this paper, a low-cost H.264/AVC video decoder design is presented for high definition television (HDTV) applications. Through optimization from algorithmic and architectural perspectives, the proposed design can achieve real-time H.264 video decoding on HD1080 video (1920 times 1088@30 Hz) when operating at 120 MHz with 320 mW power dissipation. Fabricated by using the TSMC one-poly six-metal 0.18 mum CMOS technology, the proposed design occupies 2.9times2.9 mm2 silicon area with the hardware complexity of 160K gates and 4.5K bytes of local memory
Keywords: 0.18 micron; 120 MHz; 320 mW; 4.5 kBytes; CMOS technology; H.264/AVC video decoder design; HDTV; SRAM; Si; High definition television; Low power consumption; Low-cost design; Real-time H.264 video decoding