00000cab a22000003a 4500 UP-99796217609315354 Buklod 20231007234147.0 m |o d | ta 100604s xx d | ||r ||||| || DENGII eng Miura, N. A 1 Tb s 3 W Inductive-Coupling Transceiver for 3D-Stacked Inter-Chip Clock and Data Link. pp. 111-122 A 1 Tb/s 3 W inter-chip transceiver transmits clock and data by inductive coupling at a clock rate of 1 GHz and data rate of 1 Gb/s per channel. 1024 data transceivers are arranged with a pitch of 30 mum in a layout area of 1 mm2. The total layout area including 16 clock transceivers is 2 mm2 in 0.18 mum CMOS and the chip thickness is reduced to 10 mum. Bi-phase modulation (BPM) is employed for the data link to improve noise immunity, reducing power in the transceiver. Four-phase time division multiple access (TDMA) reduces crosstalk and the bit-error rate (BER) is lower than 10-13 0.18 micron. 1 GHz. 1 Tbit/s. 3 W. CMOS integrated circuits. Bi-phase modulation. Bit-error rate. Inductive-coupling transceiver. Inter-chip transceiver. Noise immunity. System-in-package. Time division multiple access. IEEE Journal of solid state circuits 42, 1 (2007). FO UPD DENG-II Article