Hierarchical Power Distribution With Power Tree in Dozens of Power Domains for 90-nm Low-Power Multi-CPU SoCs.

Hierarchical power distribution with a power tree has been developed. The key features are a power-tree structure with three power-tree management rules and a distributed common power domain implementation. The hierarchical power distribution supports a fine-grained power gating with dozens of power...

पूर्ण विवरण

ग्रंथसूची विवरण

में प्रकाशित:	IEEE Journal of solid state circuits 42, 1 (2007).
मुख्य लेखक:	Kanno, Y.
स्वरूप:	लेख
भाषा:	English
विषय:	90 nm. Clock gating. Hierarchical power distribution. Leakage currents. Low power multiCPU SoC. Power gating. Power tree management rules. Power tree structure.