Hierarchical Power Distribution With Power Tree in Dozens of Power Domains for 90-nm Low-Power Multi-CPU SoCs. - Kanno, Y.
Hierarchical power distribution with a power tree has been developed. The key features are a power-tree structure with three power-tree management rules and a distributed common power domain implementation. The hierarchical power distribution supports a fine-grained power gating with dozens of power domains, which is analogous to a fine-grained clock gating. Leakage currents of a 1 000 000-gate power domain were effectively reduced to 1/4000 in multi-CPU SoCs with minimal area overhead
Keywords: 90 nm; Clock gating; Hierarchical power distribution; Leakage currents; Low power multiCPU SoC; Power gating; Power tree management rules; Power tree structure