A Power-Efficient High-Throughput 32-Thread SPARC Processor.

A Power-Efficient High-Throughput 32-Thread SPARC Processor.

This first generation of "Niagara" SPARC processors implements a power-efficient Chip Multi-Threading (CMT) architecture which maximizes overall throughput performance for commercial workloads. The target performance is achieved by exploiting high bandwidth rather than high frequency, ther...

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Publicat a:IEEE Journal of solid state circuits 42, 1 (2007).
Autor principal: Leon, A. S.
Format: Article
Idioma:English
Matèries:
1.2 GHz.
1.2 V.
3 MByte.
63 W.
90 nm.
CMOS technology.
DDR2 DRAM interfaces.
SPARC processor.
UltraSPARC Tl processor.
Chip multi-threading architecture.
Chip reliability.
Copper interconnect.
Interconnect crossbar.
Power management.
Shared L2 cache.
System interface unit.
Thermal management.