A 1-MHZ bandwidth 3.6-GHz 0.18-μm CMOS fractional-N synthesizer utilizing a hybrid PFD

A 1-MHZ bandwidth 3.6-GHz 0.18-μm CMOS fractional-N synthesizer utilizing a hybrid PFD

A frequency synthesizer architecture capable of simultaneously achieving high closed-loop bandwidth and low output phase noise is presented. The proposed topology uses a mismatch compensated, hybrid phase/frequency detector and digital-to-analog converter (PFD/DAC) circuit to perform active cancella...

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Publicat a:IEEE Journal of solid state circuits 41, 4 (2006).
Autor principal: Meninger, S.E
Format: Article
Idioma:English
Matèries:
0.18 micron.
1 MHz.
271 kbit/s.
3.6 GHz.
CMOS fractional-N synthesizer.
PFD/DAC circuit.
Digital-to-analog converter circuit.
Direct modulated transmitter.
Fractional-N quantization noise.
Frequency synthesizer architecture.
Hybrid PFD/DAC structure.
Hybrid phase/frequency detector.
Low output phase noise.
On-chip band select divider.
Quantization noise suppression.
Reduced broadband phase noise.
Second-order sigma-delta synthesizer.