A 20-GHz phase-locked loop for 40-gb

A 20-GHz phase-locked loop for 40-gb

A 20-GHz phase-locked loop with 4.9 pspp/0.65 psrms jitter and -113.5 dBc/Hz phase noise at 10-MHz offset is presented. A half-duty sampled-feedforward loop filter that simply replaces the resistor with a switch and an inverter suppresses the reference spur down to -44.0 dBc. A design iteration proc...

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Bibliographic Details
Published in:IEEE Journal of solid state circuits 41, 4 (2006).
Main Author: Jaeha Kim
Format: Article
Language:English
Subjects:
0.13 micron.
17.6 to 19.4 GHz.
20 GHz.
40 Gbit/s.
480 mW.
CMOS process.
Design iteration procedure.
Microstrip resonator.
Phase noise.
Phase-locked loop.
Pulsed latches.
Sampled-feedforward loop filter.
Serializing transmitter.
Static frequency dividers.