A 20-GHz phase-locked loop for 40-gb
A 20-GHz phase-locked loop with 4.9 pspp/0.65 psrms jitter and -113.5 dBc/Hz phase noise at 10-MHz offset is presented. A half-duty sampled-feedforward loop filter that simply replaces the resistor with a switch and an inverter suppresses the reference spur down to -44.0 dBc. A design iteration proc...
| الحاوية / القاعدة: | IEEE Journal of solid state circuits 41, 4 (2006). |
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| المؤلف الرئيسي: | |
| التنسيق: | مقال |
| اللغة: | English |
| الموضوعات: |