A 20-GHz phase-locked loop for 40-gb - Jaeha Kim
A 20-GHz phase-locked loop with 4.9 pspp/0.65 psrms jitter and -113.5 dBc/Hz phase noise at 10-MHz offset is presented. A half-duty sampled-feedforward loop filter that simply replaces the resistor with a switch and an inverter suppresses the reference spur down to -44.0 dBc. A design iteration procedure is outlined that minimizes the phase noise of a negative-gm oscillator with a coupled microstrip resonator. Static frequency dividers made of pulsed latches operate faster than those made of flip-flops and achieve near 2:1 frequency range. The phase-locked loop fabricated in a 0.13-μm CMOS operates from 17.6 to 19.4GHz and dissipates 480mW.
Keywords: 0.13 micron; 17.6 to 19.4 GHz; 20 GHz; 40 Gbit/s.; 480 mW; CMOS process; Design iteration procedure; Microstrip resonator; Phase noise; Phase-locked loop; Pulsed latches; Sampled-feedforward loop filter; Serializing transmitter; Static frequency dividers