A 14-bit digitally self-calibrated pipelined ADC with adaptive bias optimization for arbitrary speeds up to 40 MS

A 14-bit digitally self-calibrated pipelined ADC with adaptive bias optimization for arbitrary speeds up to 40 MS

This paper presents a 14-bit digitally self-calibrated pipelined analog-to-digital converter (ADC) featuring adaptive bias optimization. Adaptive bias optimization controls the bias currents of the amplifiers in the ADC to the minimum amount required, depending on the sampling speed, environment tem...

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书目详细资料
发表在:IEEE Journal of solid state circuits 41, 4 (2006).
主要作者: Iizuka, K.
格式: 文件
语言:English
主题:
0.18 micron.
14 bit.
19.2 mW.
2.8 V.
33.7 mW.
50.5 mW.
72.8 mW.
Adaptive bias optimization.
Analog-digital converter.
Chip fabrication.
Differential nonlinearity.
Digital calibration process.
Dual-gate CMOS technology.
Environment temperature.
Power-supply voltage.
Sampling speed.
Self-calibrated pipelined ADC.