00000cab a22000003a 4500 UP-99796217609315301 Buklod 20231007234146.0 m |o d | ta 100603s xx d | ||r ||||| || DENGII eng Fa Foster Dai A direct digital frequency synthesizer with fourth-order phase domain ΔΣ noise shaper and 12-bit current-steering DAC. pp. 839-850 This paper presents a direct digital frequency synthesizer (DDFS) with a 16-bit accumulator, a fourth-order phase domain single-stage ΔΣ interpolator, and a 300-MS/s 12-bit current-steering DAC based on the Q2 Random Walk switching scheme. The ΔΣ interpolator is used to reduce the phase truncation error and the ROM size. The implemented fourth-order single-stage ΔΣ noise shaper reduces the effective phase bits by four and reduces the ROM size by 16 times. The DDFS prototype is fabricated in a 0.35-μm CMOS technology with active area of 1.11mm2 including a 12-bit DAC. The measured DDFS spurious-free dynamic range (SFDR) is greater than 78 dB using a reduced ROM with 8-bit phase, 12-bit amplitude resolution and a size of 0.09 mm2. The total power consumption of the DDFS is 200mW with a 3.3-V power supply. 0.35 micron. 12 bit. 16 bit. 200 mW. 3.3 V. 8 bit. CMOS technology. DDFS prototype. ROM size. Current-steering DAC. Delta-sigma noise shaper. Direct digital frequency synthesizer. Fourth-order phase domain noise shaper. Phase truncation error. Random walk switching scheme. Single-stage delta-sigma interpolator. Spurious-free dynamic range. IEEE Journal of solid state circuits 41, 4 (2006). FO UPD DENG-II Article