Design on ESD protection scheme for IC with power-down-mode operation.

This paper presents a new electrostatic discharge (ESD) protection scheme for IC with power-down-mode operation. Adding a VDD ESD bus line and diodes into the proposed ESD protection scheme can block the leakage current from I/O pin to VDD power line and avoid malfunction during power-down operation...

Disgrifiad llawn

Manylion Llyfryddiaeth
Cyhoeddwyd yn:	IEEE Journal of solid state circuits 39, 8 (2004).
Prif Awdur:	Ming-Dou Ker
Fformat:	Erthygl
Iaith:	English
Pynciau:	0.35 micron. 7.5 kV. ESD clamp circuits. ESD protection design. ESD protection scheme. HBM ESD level. I/O pin. IC protection. VDD ESD bus line. VDD ESD diodes. VDD power line. VSS power line. Electrostatic discharge. Human-body model. Leakage current. Power-down mode. Power-down-mode operation. Silicided CMOS process.