A 3.125-Gb
A 3.125-Gb/s clock and data recovery (CDR) circuit using a half-rate digital quadricorrelator frequency detector and a shifted-averaging voltage-controlled oscillator is presented for 10-Gbase-LX4 Ethernet. It can achieve low-jitter operation and improve pull-in range without a reference clock. This...
| 發表在: | IEEE Journal of solid state circuits 39, 8 (2004). |
|---|---|
| 主要作者: | |
| 格式: | Article |
| 語言: | English |
| 主題: |