A 3.125-Gb

A 3.125-Gb/s clock and data recovery (CDR) circuit using a half-rate digital quadricorrelator frequency detector and a shifted-averaging voltage-controlled oscillator is presented for 10-Gbase-LX4 Ethernet. It can achieve low-jitter operation and improve pull-in range without a reference clock. This...

Descripció completa

Dades bibliogràfiques
Publicat a:	IEEE Journal of solid state circuits 39, 8 (2004).
Autor principal:	Rong-Jyi Yang
Format:	Article
Idioma:	English
Matèries:	0.18 micron. 1.8 V. 10-Gbase-LX4 Ethernet. 3.125 Gbit/s. 83 mW. CMOS technology. Bit-error rate. Clock recovery circuit. Data recovery circuit. Half-rate digital quadricorrelator frequency detector. Jitter tolerance specifications. Low-jitter operation. Pull-in range. Reference clock. Shifted-averaging voltage-controlled oscillator.