Low-power pipeline ADC for wireless LANs.
In this paper, a 10-bit 40-MS/s analog-to-digital converter (ADC) is presented. A power consumption of 12 mW was achieved by using a time-interleaved and pipelined architecture with shared operational amplifiers. This circuit was fabricated in a 2.5-V 0.25-μm technology with metal-oxide-metal capaci...
| Cyhoeddwyd yn: | IEEE Journal of solid state circuits 39, 8 (2004). |
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| Prif Awdur: | |
| Fformat: | Erthygl |
| Iaith: | English |
| Pynciau: |