A 10-b 150-MSample/s 1.8-V 123-mW CMOS A - Jong-Bum Park
This work describes a 10-b 150-MSample/s 4-b-per-stage single-channel CMOS pipelined ADC incorporating improved gate-bootstrapping techniques for a wideband SHA and temperature- and supply-insensitive CMOS references. The proposed ADC is designed and fabricated in a 0.18-μm one-poly six-metal CMOS technology. The measured differential and integral nonlinearities are within 0.69 LSB and 1.50 LSB, respectively. The prototype ADC shows a peak signal-to-noise-and-distortion ratio (SNDR) of 52 dB at 150 MSample/s. The ADC maintains the SNDR over 52 dB and 43 dB, respectively, for input frequencies up to the Nyquist frequency and 400 MHz at 140 MSample/s. The active die area is 2.2 mm2 and the chip consumes 123 mW at 150 MSample/s.
Keywords: 0.18 micron; 1.8 V; 10 bit; 123 mW; 400 MHz; CMOS A/D converter; Nyquist frequency; Analog-to-digital converters; Differential nonlinearities; Gate-bootstrapping techniques; Input bandwidth; Input frequencies; Integral nonlinearities; One-poly six-metal CMOS technology; Pipelined ADC; Signal-to-noise-and-distortion ratio; Single-channel ADC; Supply-insensitive CMOS references; Temperature-insensitive CMOS references; Wideband SHA