A low-power DS-CDMA RAKE receiver utilizing resource allocation techniques.

A low-power DS-CDMA RAKE receiver utilizing resource allocation techniques.

This paper presents architectural and implementation innovations made to realize a self-contained front-end processor for any DS-CDMA-based system. At the heart of the ASIC is a highly flexible RAKE processing engine that utilizes a unique resource allocation technique for maximum flexibility. The f...

Disgrifiad llawn

Manylion Llyfryddiaeth
Cyhoeddwyd yn:IEEE Journal of solid state circuits 39, 8 (2004).
Prif Awdur: Eltawil, A.M
Fformat: Erthygl
Iaith:English
Pynciau:
0.18 micron.
3G cellular radio.
4.032 mW.
ASIC.
CMOS.
DS-CDMA-based system.
RAKE processing engine.
RAKE receiver.
Architectural innovations.
Channel correction.
Channel estimation.
Data tagging.
Design reuse.
Digital timing.
Direct digital frequency synthesis.
Firmware control.
Frequency recovery circuits.
Frequency recovery loop.
Front-end processor.
Interpolation.
Microcontroller interface.
Multipath combiner.
Multipath searcher.
Power consumption.
Resource allocation.
System resources.