A test circuit for measurement of clocked storage element characteristics.

A test circuit for measurement of clocked storage element characteristics.

We present a method, on-chip test circuitry, and an error analysis, for accurate measurement of timing characteristics and power consumption of clocked storage elements. The test circuit was fabricated in 0.11 μm CMOS technology and the measurements performed automatically using a serial scan interf...

詳細記述

書誌詳細
出版年:IEEE Journal of solid state circuits 39, 8 (2004).
第一著者: Nedovic, N.
フォーマット: 論文
言語:English
主題:
0.11 micron.
CMOS.
Clock-to-output characteristics.
Clocked storage elements.
Data-to-output delay.
Error analysis.
Flip-flops.
Measurement circuit.
On-chip measurement.
On-chip test circuitry.
Power consumption.
Random error.
Serial scan interface.
Systematic measurement error.
Test circuit.
Timing characteristics.