Power optimized partial scan BIST implementation on DLX microprocessor - Buenaventura, Arvi D.; Miranda, Carlos Miguel A.; Salvacion, Ma. Katrina D. (2010)
The need for efficient chip testing methods is needed as integrated circuits become more complex. Together with this is the increase in costs in terms of time and monetary resources with the use of external Automated Test Equipment (ATEs). One alternative is the incorporation of a Built-in Self-test (BIST) circuit into the chip design. Previous studies have indicated the potential of adding BIST capability to microprocessors in achieving high fault coverage at reduced testing cost. These improvements, however, came at the expense of increased power consumption and die area, and reduced performance. The objective of the project is to implement a BIST architecture for the DLX microprocessor that has less impact on the power consumption and with minimal effect on the overall performance. This involves applying a partial scan methodology and implementing power optimization techniques on the design. The power optimization technique includes some gating logic for masking the scan path activity during shifting and synthesizing additional logic for suppressing random patterns that do not contribute in increasing the fault coverage of the test. The implemented microprocessor is compared to the unmodified DLX microprocessor and to the DLX microprocessor with power optimized partial scan BIST. The comparison is done in terms of area, speed, and power consumption. In normal mode, the DLX with partial scan BIST was observed to have a negligible difference on performance compared with the base DLX. Also, the area only increased by 8.55% and the power by 15.14% with respect to the base DLX core.
Thesis (B.S. Computer Engineering) -- University of the Philippines, Diliman
Keywords: Microprocessors; Automatic test equipment; DLX microprocessor