Design and implementation of pipelined analog-to-digital converters in a 90nm CMOS process - Dizon, Aaron Galvez
Digital signal processing makes use of analog-to-digital converters (ADCs) to transform analog signals into digital information that can be processed to suit a specific application. Imaging, instrumentation, video, and communication applications commonly utilize pipelined ADCs due to its high speed and high bandwidth capabilities. The aim of this project is to design, implement, and compare 8-bit pipelined ADCs. Each pipelined stage consists of a sample-and-hold circuit, a sub-stage ADC, difference amplifier, and a DAC. Digital circuits consisting of a clock and delay flip-flops were connected to the stages to implement the whole pipelined ADC. The delay flip-flops were used to synchronize the digital output bits from each pipeline stage. The 1.5-bit per stage Redundant Signed Digit technique was employed to improve the ADC's accuracy. This technique was implemented using a Carry-Look Ahead Full Adder. This project includes the Commutated Feedback Capacitor Switching and Operational Amplifier optimization techniques for overall performance comparison with the conventional. Three 8-bit, 10 MS/s pipelined ADCs operating at IV supply are described. Dynamic parameters were obtained using a 0.8Vpp, 1 MHz input sinusoid. The conventional ADC achieved a DNL of [0, +4] and an INL of [-5, +36]. Applying the CFCS technique in the schematic implementation has successfully reduced the ADC's maximum INL by 8 LSB. However, the CFCS ADC layout had the worst linearity due to the increase in the number of switches and flip-flops. The conventional ADC used 9.16 mW of power and 0.624 µm² of area. A lower power consumption of 5.16 mW and lower chip area of 0.578 µm² was achieved using the OAS technique. The correspond to 43.67% reduction in power and 7.37% decrease in chip area.