A single-chip digitally calibrated 5.15-5.825-GHz 0.18-μm CMOS transceiver for 802.11a wireless LAN. - Vassiliou, I.
The drive for cost reduction has led to the use of CMOS technology in the implementation of highly integrated radios. This paper presents a single-chip 5-GHz fully integrated direct conversion transceiver for IEEE 802.11a WLAN systems, manufactured in 0.18-μm CMOS. The IC features an innovative system architecture which takes advantage of the computing resources of the digital companion chip in order to eliminate I/Q mismatch and achieve accurately matched baseband filters. The integrated voltage-controlled oscillator and synthesizer achieve an integrated phase noise of less than 0.8° rms. The receiver has an overall noise figure of 5.2 dB and achieves sensitivity of -75 dBm at 54-Mb/s operation, both referred to the IC input. The transmit error vector magnitude is -33 dB at -5-dBm output power from the integrated power-amplifier driver amplifier. The transceiver occupies an area of 18.5 mm2.
Keywords: 5.15 to 5.825 GHz; 5.2 dB; 54 Mbit/s.; 802.11a standard; CMOS technology; I/Q mismatch elimination; IC input; IEEE 802.11a.; OFDM; RF CMOS; RF transceiver; SoC; WLAN systems; Baseband filters; Cost reduction; Digital calibration; Digital companion chip; Integrated phase noise; Integrated power amplifier-driver amplifier; Integrated radios; Integrated voltage-controlled oscillator; Orthogonal frequency division multiplexing; Single-chip 5-GHz fully integrated direct conversion transceiver; Synthesizer; System architecture; System-on-a-chip.; Transmit error vector magnitude; Wireless LAN; 0.18-μm CMOS transceiver